1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having flip-flop memory cells and, more particularly, to a technique of controlling the voltage of a word line.
2. Description of the Related Art
In recent years, as the process rule is reduced, the areas and the power supply voltages of semiconductor integrated circuits are rapidly reduced. This leads to detrimental effects. For example, in a semiconductor integrated circuit having flip-flop memory cells, such as a static random access memory (hereinafter referred to as an SRAM), it has been considerably difficult to impart stable characteristics to the memory cells due to variations in characteristics of transistors included in the memory cells or the reduction of the power supply voltage. As a result, the yield of the semiconductor integrated circuit is reduced.
In general, it is known that the threshold voltage Vt of a transistor varies in proportion to 1/√(W×L), where W is the width of the transistor and L is the length of the transistor. In other words, as the transistor width W and the transistor length L are reduced with a reduction in the process rule, a variation in the transistor threshold voltage Vt becomes more significant.
Thus, when the reduced process rule is used, it is considerably important to suppress variations in elements included in a semiconductor integrated circuit in order to achieve stable characteristics and performance of the semiconductor integrated circuit.
SRAMs have a static noise margin (hereinafter also referred to as an SNM) as a characteristic of a memory cell. The SNM is an index indicating the magnitude of a margin with respect to noise. The larger the value of the SNM, the higher the data holding performance of the memory cell (e.g., as data held in a flip-flop of a memory cell becomes more unlikely to be inverted due to noise from a bit line pair when a word line is in the active state, the data holding performance becomes higher). The SNM is generally improved by reducing the conductance of an access transistor included in a memory cell of an SRAM.
As a technique of improving the SNM, the following examples are known. Japanese Unexamined Patent Application Publication No. 2002-368135 (Patent Document 1) describes that different power supply voltages are supplied separately to a peripheral circuit and a memory array of an SRAM (a power supply voltage for the peripheral circuit is set to be lower than a power supply voltage for the memory array). It is also described that a step-up power supply circuit or a step-down power supply circuit is provided so as to cause the power supply voltage for the peripheral circuit to be lower than the power supply voltage for the memory array.
A word line for controlling the gate terminal of the access transistor is driven by a power supply for the peripheral circuit of the SRAM. Therefore, the voltage of the word line in the active state is lower than the power supply voltage for the memory array. Therefore, the conductance of the access transistor controlled by the word line is reduced, resulting in an improvement in the SNM.
Also, Japanese Unexamined Patent Application Publication No. 2005-276277 (Patent Document 2) describes that a transfer gate including an n-channel metal oxide semiconductor transistor (hereinafter referred to as an NMOS transistor) and a p-channel metal oxide semiconductor transistor (hereinafter referred to as a PMOS transistor) is connected in series to a word line. The voltage value of the word line in the active state is controlled to be lower by an amount corresponding to the threshold voltage of the NMOS transistor than the power supply voltage, so that the conductance of the access transistor is reduced, resulting in an improvement in the SNM.
However, if two different power supply voltages cannot be supplied to an SRAM (only one power supply voltage is supplied), a method as described in Patent Document 1 cannot be used.
Also, if a step-up power supply circuit or a step-down power supply circuit is provided as in Patent Document 1, a power supply for the whole peripheral circuit or the whole memory array is controlled, resulting in an increase in power consumption. The provision of a step-up power supply circuit or a step-down power supply circuit also leads to an increase in layout area of the whole circuit.
If a transfer gate is used as in Patent Document 2, the voltage value of a word line in the active state can be set to be lower only by an amount corresponding to the threshold voltage of the NMOS transistor than the power supply voltage. Also, the transfer gate is connected in series to a word driver circuit for driving the word line, and therefore, the capability to drive the word line is reduced, leading to a deterioration in the rising or falling speed of the word line voltage.
Further, if the word line is caused to be in the active state for a long period of time, the word line voltage goes up to the power supply voltage level due to a leakage current via the transfer gate or the like. In other words, the word line voltage cannot be controlled to have a desired value (a value lower by an amount corresponding to the threshold voltage of the NMOS transistor than the power supply voltage). The influence of variations in elements constituting the circuit is not taken into consideration, and therefore, when the reduced process rule is used, it is considerably difficult to achieve the stable characteristics and performance of the semiconductor integrated circuit.